// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

  .section .text

exception_handler:
  jal x0, exception_handler

default_irq_handler:
  jal x0, default_irq_handler

reset_handler:
  /* set all registers to zero */
  mv  x1, x0
  mv  x2, x1
  mv  x3, x1
  mv  x4, x1
  mv  x5, x1
  mv  x6, x1
  mv  x7, x1
  mv  x8, x1
  mv  x9, x1
  mv x10, x1
  mv x11, x1
  mv x12, x1
  mv x13, x1
  mv x14, x1
  mv x15, x1
  mv x16, x1
  mv x17, x1
  mv x18, x1
  mv x19, x1
  mv x20, x1
  mv x21, x1
  mv x22, x1
  mv x23, x1
  mv x24, x1
  mv x25, x1
  mv x26, x1
  mv x27, x1
  mv x28, x1
  mv x29, x1
  mv x30, x1
  mv x31, x1

  /* stack initilization */
  la   x2, _stack_start

_start:
  .global _start

  /* clear BSS */
  la x26, _bss_start
  la x27, _bss_end

  bge x26, x27, zero_loop_end

zero_loop:
  sw x0, 0(x26)
  addi x26, x26, 4
  ble x26, x27, zero_loop
zero_loop_end:


main_entry:
  /* jump to main program entry point (argc = argv = 0) */
  addi x10, x0, 0
  addi x11, x0, 0
  jal x1, main

/* ====================== [ exceptions & interrupts ] =================== */
/* This section has to be down here, since we have to disable rvc for it  */

  .section .vectors, "ax"
  .option norvc;

  // exception handler
  .org 0x00
  jal x0, exception_handler

  /* use the same default handler for all interrupts */
  // software interrupt handler
  .org 0x0c
  jal x0, default_irq_handler

  // timer interrupt handler
  .org 0x1c
  jal x0, default_irq_handler

  // external interrupt handler
  .org 0x2c
  jal x0, default_irq_handler

  // fast interrupts 0 - 14
  .org 0x40
  .rept 14
  nop
  .endr
  jal x0, default_irq_handler

  // non-maskable interrupt handler
  .org 0x7c
  jal x0, default_irq_handler

  // reset vector
  .org 0x80
  jal x0, reset_handler
